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| ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58SM/LMxxxATA-Disk Module 8MB / 16MB / 24MB / 32MB / 48MB / 64MB / 96MB / 128MB / 192MB Advance Information FEATURES: * ATA/IDE standard interface - 512 Bytes per sector - ATA command set compatible - Selectable Master/Slave Operation - Support Data Transfer Speed up to PIO Mode-4 * 8, 16, 24, 32, 48, 64, 96, 128, and 192 MByte capacities * Standard Female IDE Connector - 40-pin and 44-pin * Single Voltage Read and Write Operation - 5.0V-only for SST58SMxxx - 3.3V-only for SST58LMxxx * Supports 5.0-Volt or 3.3-Volt Read and Write - 4.5-5.5V or 3.135-3.465V for Commercial * Low Power Consumption - Active mode: 35 mA/55 mA (3.3V/5.0V) (typical) - Sleep mode: 100 A/150 A (3.3V/5.0V) (typical) * Sustained Write Performance - Up to 1.4 MB/sec (host to flash) * Extended Data Protection and Security - WP# pin for Data Protection - Factory-Programmed, 20-Byte Unique ID number * Controller Overhead Command to DRQ - Less than 0.5 ms * Zero Power Data Retention - Batteries not required for data storage * Start Up Time - Sleep to read: 200 ns (typical) - Sleep to write: 200 ns (typical) - Power-on to Ready:200 ms (typical) * Support for Commercial Temperature Range - 0C to +70C for Operating Commercial - -50C to +100C for non-Operating (storage) * Extremely Rugged and Reliable - Built-in ECC support corrects 3 Bytes of error per 512 Byte sector * Intelligent ATA/IDE Controller - Built-in microcontroller with intelligent firmware - Built-in Embedded Flash File System * Power Management Unit - Immediate disabling of unused circuitry PRODUCT DESCRIPTION SST's ATA-Disk Module (ADM) is a low cost, high performance, embedded flash memory data storage system. This product is well suited for solid state mass storage applications offering new and expanded functionality while enabling cost effective designs. The ADM is a solid state disk drive that is designed to replace conventional IDE hard disk drive and can be plugged into a standard IDE connector commonly found in desktop or portable PC systems. ADM has built-in microcontroller and file management firmware that communicates with ATA standard interfaces; therefore, the ADM does not require additional or proprietary host software such as Flash File System (FFS) and Memory Technology Driver (MTD) software. The ADM is designed to work at either 5V or 3.3V and is available in 8 to 192 MByte capacities. It uses standard ATA driver that is part of all major OS such as Windows 95/98/ 2000/NT/CE, MAC, UNIX, etc. All signals, except WP#, are in compliance with the ATA specifications. WP# is used to write protect the information stored on the ADM. The WP# could be connected to the motherboard write protect control logic through a jumper. When WP# is low, the ADM is write protected to prohibit any inadvertent writes. Every ADM comes with factory-programmed, 20-Byte long, unique identification number for extended data protection. This feature prevents unauthorized duplication by allowing encryption of customer data. The ADM integrates a standard 40- or 44-pin female connector for easy and cost effective mounting on top of a standard IDE male connector commonly found on the system motherboards. ADM also offers user selectable Master/Slave operation through an external jumper setting. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information TABLE OF CONTENTS PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.0 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Performance-optimized ATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 Microcontroller Unit (MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Flash File System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 5 5 1.2 SST's ATA-Disk Module Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 ELECTRICAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0.1 Pin Assignment and Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Electrical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 Absolute Maximum Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Drive Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Input (Read) Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Output (Write) Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 11 11 12 13 2.4 I/O Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0 SOFTWARE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 ATA-Disk Module Drive Register Set Definitions and Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 ATA-Disk Module Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 ATA-Disk Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.1 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.2 Error Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.3 Feature Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.4 Sector Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.5 Sector Number (LBA 7-0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.6 Cylinder Low (LBA 15-8) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.7 Cylinder High (LBA 23-16) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.8 Drive/Head (LBA 27-24) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.9 Status & Alternate Status Registers (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.10 Device Control Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.11 Drive Address Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.12 Command Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 16 16 16 16 16 16 17 17 18 18 (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 2 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2 ATA-Disk Module Command Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 ATA-Disk Module Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.1 Check Power Mode - 98H or E5H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.2 Execute Drive Diagnostic - 90H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.3 Format Track - 50H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4 Identify Drive - ECH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.1 General Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.2 Default Number of Cylinders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.3 Default Number of Heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.4 Default Number of Sectors per Track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.5 Number of Sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.6 Memory Serial Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.7 Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.8 Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.9 ECC Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.10 Firmware Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.11 Model Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.12 Read/Write Multiple Sector Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.13 Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.14 PIO Data Transfer Cycle Timing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.15 Translation Parameters Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.16 Current Number of Cylinders, Heads, Sectors/Track . . . . . . . . . . . . . . . . . . . 3.2.1.4.17 Current Capacity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.18 Multiple Sector Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.19 Total Sectors Addressable in LBA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.20 Advanced PIO Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.4.21 Minimum PIO Transfer Cycle Time Without Flow Control . . . . . . . . . . . . . . . 3.2.1.4.22 Minimum PIO Transfer Cycle Time with IORDY. . . . . . . . . . . . . . . . . . . . . . . 3.2.1.5 Idle - 97H or E3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.6 Idle Immediate - 95H or E1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.7 Initialize Drive Parameters - 91H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.8 Read Buffer - E4H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.9 Read Multiple - C4H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.10 Read Long Sector - 22H or 23H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.11 Read Sectors - 20H or 21H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.12 Read Verify Sector(s) - 40H or 41H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.13 Recalibrate - 1XH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.14 Seek - 7XH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.15 Set Features - EFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.16 Set Multiple Mode - C6H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.17 Set Sleep Mode - 99H or E6H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.18 Standby - 96H or E2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.19 Standby Immediate - 94H or E0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.20 Write Buffer - E8H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.21 Write Long Sector - 32H or 33H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.22 Write Multiple Command - C5H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.23 Write Sector(s) - 30H or 31H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.24 Write Verify - 3CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Error Posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 20 21 21 23 23 23 23 23 23 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 25 25 25 26 26 27 27 28 28 28 29 30 30 31 31 31 32 32 33 33 34 (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 3 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 4.0 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1 Differences between ATA-Disk Module and ATA/ATAPI-5 Specifications. . . . . . . . . . . . . . . . . . . . . . . 35 4.1.1 Electrical Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1.1 TTL Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1.2 Pull Up Resistor Input Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Functional Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2.1 Idle Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2.2 Recovery from Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 35 35 35 5.0 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.0 LIMITED WARRANTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 Life Support Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 Patent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 4 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 1.0 GENERAL DESCRIPTION The SST's ATA-Disk Module (ADM) contains a controller, embedded firmware, and Flash Media with a 40-pin or 44pin female connector. Refer to Figure 1-1 for SST's ADM block diagram. The controller interfaces with the host system allowing data to be written to and read from the Flash Media. 1.1.3 Power Management Unit (PMU) Power Management Unit controls the power consumption of the ADM. The PMU dramatically extends product battery life by putting the part of the circuitry that is not in operation into sleep mode. 1.1.4 SRAM Buffer 1.1 Performance-optimized ATA Controller The heart of the ADM is the ATA controller which translates standard ATA signals into Flash Media data and controls. SST's ADM contains a proprietary ATA controller specifically designed to attain high data throughput from host to Flash. The following components contribute to the ATA controller's performance. 1.1.1 Microcontroller Unit (MCU) The MCU translates ATA commands into data and control signals required for flash memory operation. 1.1.2 Internal Direct Memory Access (DMA) The ATA controller inside ADM uses DMA allowing instant data transfer from buffer to memory. This implementation eliminates microcontroller overhead associated with traditional, firmware based, memory control, increasing data transfer rate. A key contributor to the ATA controller performance is an SRAM buffer. The buffer optimizes the data writes to Flash. 1.1.5 Embedded Flash File System Embedded Flash File System is an integral part of the SST's ATM controller. It contains MCU Firmware that performs the following tasks: 1. Translates host side signals into Flash Media Writes and Reads. 2. Provides Flash Media wear leveling to spread the Flash writes across all the memory address space to increase the longevity of Flash Media. 3. Keeps track of data file structures. 1.1.6 Error Correction The ATA Controller contains ECC algorithm that corrects 3 bytes of error per 512 Byte sector. 40 or 44-Pin Male IDE Connector 40 or 44-Pin Female IDE Connector ATA-Disk Module ATA Controller PC Mother Board Embedded Flash File System SRAM Buffer MCU ECC Internal DMA PMU Flash Media 519 ILL1-1.4 FIGURE 1-1: SST ATA-DISK MODULE BLOCK DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 5 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 1.2 SST's ATA-Disk Module Product Offering The SST58SM/LMxxx ATA-Disk Module product family is available in 8 to 192 MByte densities. The following table shows the specific capacity, default number of cylinder heads, sectors and cylinders for each product line. Model Number SST58SM/LM008 SST58SM/LM016 SST58SM/LM024 SST58SM/LM032 SST58SM/LM048 SST58SM/LM064 SST58SM/LM096 SST58SM/LM128 SST58SM/LM192 Density 8 MB 16 MB 24 MB 32 MB 48 MB 64 MB 96 MB 128 MB 192 MB Total Bytes 8,028,160 16,023,552 24,051,712 32,047,104 48,037,888 64,028,672 96,075,776 128,057,344 192,151,552 Cylinders 245 489 367 489 733 977 733 977 733 Heads 2 2 4 4 4 4 8 8 16 Sectors 32 32 32 32 32 32 32 32 32 2.0 ELECTRICAL INTERFACE 2.0.1 Pin Assignment and Pin Type The signal/pin assignments are listed in Tables 2-1 and 2-2. Low active signals have a "#" suffix. Pin types are Input, Output or Input/Output. Section 2.3 defines the DC characteristics for all input and output type structures. 2.1 Electrical Description The ADM functions in ATA Mode, which is compatible with IDE hard disk drives. Table 2-3 describes the I/O signals. Signals whose source is the host are designated as inputs while signals that the ADM sources are outputs. All outputs from the ADM are totem pole except the data bus signals which are in the bi-directional tri-state. Refer to Section 2.3.2 for definitions of Input and Output types. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 6 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information TABLE Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 2-1: 44-PIN PIN ASSIGNMENT Signal Name RESET# GND D7 D8 D6 D9 D5 D10 D4 D11 D3 D12 D2 D13 D1 D14 D0 D15 GND NC NC GND IOWR# GND IORD# GND NC NC2 NC NC/WP#3 INTRQ IOCS16# A1 PDIAG# A0 A2 CS1FX# CS3FX# DASP# GND VDD VDD GND NC T2-1.6 519 TABLE I/O Type1 I4U Ground I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 Ground 2-2: 40-PIN PIN ASSIGNMENT Signal Name RESET# GND D7 D8 D6 D9 D5 D10 D4 D11 D3 D12 D2 D13 D1 D14 D0 D15 GND VDD2 NC GND IOWR# GND IORD# GND NC NC3 NC NC/WP#4 INTRQ IOCS16# A1 PDIAG# A0 A2 CS1FX# CS3FX# DASP# GND O O I I/O I I I I I/O I2U O1 O2 I2D I2U, O1 I2D I2D I3U I3U I2U, O1 Ground T2-2.6 519 Pin Type I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin Type I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type1 I4U Ground I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 I2D, O2 Ground Power Ground Ground I I I3U Ground I3U Ground I I I3U Ground I3U Ground I2U O O I I/O I I I I I/O O1 O2 I2D I2U, O1 I2D I2D I3U I3U I2U, O1 Ground Power Power Ground 28 29 30 31 32 33 34 35 36 37 38 39 40 1. Please refer to Sections 2.3.1 to 2.3.4 for detail 2. Pin 28 is CSEL in standard host 40-pin IDE interface. Master/ Slave setting is selected through an on-board jumper. 3. Pin 30 is jumper selectable as NC or WP#. 1. Please refer to Sections 2.3.1 to 2.3.4 for detail. 2. Optional, not available in standard host 40-pin IDE interface. 3. Pin 28 is CSEL in standard host 40-pin IDE interface. Master/ Slave setting is selected through an on-board jumper. 4. Pin 30 is jumper selectable as NC or WP#. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 7 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information TABLE 2-3: SIGNAL DESCRIPTION Type1 I I/O Pin 33,34,35 18,16,14,12,10, 8,6,4,3,5,7,9,11, 13,15,17 37,38 28 Name and Functions A[2:0] are used to select one of the Task File registers. Data bus Symbol A2 - A0 D15 - D0 CS1FX#, CS3FX# CSEL I - CS1FX# is the chip select for the task file registers while CS3FX# is used to select the Alternate Status Register and the Device Control Register. CSEL signal is a NC to the motherboard. The Master/Slave selection is set by a jumper. If the jumper is in a Master position, the ADM is addressed as a Master drive, and if the jumper is in a Slave position, the ADM is addressed as a Slave drive. This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the chip. The I/O Write strobe pulse is used to clock I/O data into the chip. This output signal is asserted low when this device is expecting a word data transfer cycle. Signal is the active high Interrupt Request to the host. This input/output is the Pass Diagnostic signal in the Master/Slave handshake protocol. This input/output is the Disk Active/Slave present signal in the Master/Slave handshake protocol. This input pin is the active low hardware reset from the host. Ground Write protect pin is used to disable Write operation. The 3-position jumper can set pin 30 as NC, write protected (by connecting to GND), or host selectable (by connecting to pin 30 of IDE connector). When the signal on this pin is low, data on the chip will be write-protected. (See Figure 2-1) Power T2-3.6 519 IORD# IOWR# IOCS16# INTRQ PDIAG# DASP# RESET# GND WP#3 I I O O I/O I/O I I 25 23 32 31 34 39 1 2,19,22,24,26, 30,40,432 30 VDD 1. 2. 3. 4. - 204, 412, 422 Please refer to Sections 2.3.1 to 2.3.4 for detail Only available with the 44-pin connector module Pin 30 is jumper selectable as NC or WP# Only available with the 40-pin connector module For the 40-pin ATA-Disk Module, power can be supplied either through the pin 20 (not present on standard 40-pin IDE interface) or through the external power connector provided on the 40-pin ADM. Please see the drawings in "Physical Dimensions" on page 36 for information. ATA-Disk Module WP# Jumper Pin 30 3 2 1 ATA Controller Flash Memory WP# Jumper ATA-Disk Module No Jumper Close 1, 2 Close 2, 3 NC, Module is NOT write protected. Connect to Ground, Module is write protected Host Selectable, Module is write protected if pin 30 is low. Module is NOT write protected if pin 30 is high. T2-3.0 519 519 ILL2-5.1 FIGURE 2-1: PIN 30 CONFIGURATION S71193-01-000 9/01 519 (c)2001 Silicon Storage Technology, Inc. 8 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 2.2 Absolute Maximum Stress Ratings Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50C to +100C D.C. Voltage on any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE: SST58SMXXX Range Commercial Ambient Temp 0C to +70C VDD 4.5-5.5V OPERATING RANGE: SST58LMXXX Range Commercial Ambient Temp 0C to +70C VDD 3.135-3.465V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figure 2-3 Note: All AC specifications are guaranteed by design. TABLE Symbol TPU-READY1 TPU-WRITE1 2-4: RECOMMENDED SYSTEM POWER-UP TIMINGS Parameter Power-up to Ready Operation Power-up to Program/Erase Operation Maximum 500 500 Units ms ms T2-4.0 519 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 9 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 2.3 Electrical Specification The following tables define all D.C. Characteristics for the SST ATA-Disk Module product family. 2.3.1 Absolute Maximum Conditions Unless otherwise stated, conditions are for Commercial Temperature: Non-operating (storage) temperature range: -50C to +100C VDD = 4.5-5.5V VDD = 3.135-3.465V Ta = 0C to +70C ABSOLUTE MAXIMUM CONDITIONS Parameter Input Power Voltage on any pin except VDD with respect to GND Symbol VDD V Conditions -0.3V min to 6.5V max -0.5V min to VDD + 0.5V max INPUT POWER Voltage 3.135-3.465V 4.5-5.5V Maximum Average RMS Active Current 75 mA 100 mA Maximum Average RMS Sleep Current 200 A 300 A Measurement Method 3.3V at 25C1 5.0V at 25C1 1. Current measurement is accomplished by connecting an amp meter (set to the 2 amp scale range) in series with the VDD supply to the ADM. Current measurements are to be taken while looping on a data transfer command with a sector count of 128. Current consumption values for both Read and Write commands are not to exceed the Maximum Average RMS Current specified in the above table. ADM products shall operate correctly in both voltage ranges as shown in the tables above. To comply with this specification, current requirements must not exceed the maximum limit. 2.3.2 Input Leakage Current In the table below, x refers to the characteristics described in Section 2.3.2. For example, I1U indicates a pull up resistor with a type 1 input characteristic. Type IxZ IxU IxD Parameter Input Leakage Current Pull Up Resistor Pull Down Resistor Symbol IL RPU1 RPD1 Conditions VIH = VDD / VIL = Gnd VDD = 5.0V VDD = 5.0V MIN -1 50k 50k TYP MAX 1 500k 500k Units A Ohm Ohm (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 10 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 2.3.3 Input Characteristics Min Type 1 2 3 Parameter Input Voltage CMOS Input Voltage CMOS Input Voltage CMOS Schmitt Trigger 4 Input Voltage CMOS Schmitt Trigger VTH VTL 1.8 0.9 2.4 0.8 Volts Symbol VIH VIL VIH VIL VTH VTL 2.0 0.5 2.0 0.8 2.4 0.8 2.4 0.6 2.7 0.8 Volts Typ VDD = 3.3V 2.4 0.8 Volts Max Min Typ VDD = 5.0V Max Units Volts 2.3.4 Output Drive Type All output drive type are CMOS level. 2.3.5 Output Drive Characteristics Type O1 O2 Parameter Output Voltage Output Voltage Symbol VOH VOL VOH VOL Conditions IOH = -4 mA IOL = 4 mA IOH = -8 mA IOL = 8 mA VDD-0.8V Gnd+0.4V MIN VDD-0.8V Gnd+0.4V Volts TYP MAX Units Volts (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 11 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 2.3.6 I/O Input (Read) Timing Specification TABLE Item Data Setup before IORD# Data Hold following IORD# IORD# Width Time Valid Address Setup before IORD# Valid Address Hold following IORD# IOCS16# Delay Falling from Address IOCS16# Delay Rising from Address 2-5: I/O READ TIMING Symbol tsu(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tdfIOCS16(ADR) tdrIOCS16(ADR) IEEE Symbol tDVIRH tlGHQX tlGLIGH tAVIGL tlGHAX tAVISL tAVISH Min 20 5 70 25 10 Max 20 20 T2-5.4 519 Note: All times are in nanoseconds. The maximum load on IOCS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. Valid Address1 tsuA(IORD) tw(IORD) thA(IORD) tdrIOCS16(ADR) tsu (IORD) IORD# IOCS16# tdfIOCS16(ADR) th(IORD) Dout 519 ILL2-7.3 D15-D0 1. Valid Address consists of signals CS1FX#, CS3FX#, and A2-A0. FIGURE 1: I/O READ TIMING DIAGRAM (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 12 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 2.3.7 I/O Output (Write) Timing Specification TABLE Item Data Setup before IOWR# Data Hold following IOWR# IOWR# Width Time Valid Address Setup before IOWR# Valid Address Hold following IOWR# IOCS16# Delay Falling from Address IOCS16# Delay Rising from Address 2-6: I/O WRITE TIMING Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tdfIOCS16(ADR) tdrIOCS16(ADR) IEEE Symbol tDVIWH tlWHDX tlWLIWH tAVIWL tlWHAX tAVISL tAVISH Min 20 10 70 25 10 Max 20 20 T2-6.4 519 Note: All times are in nanoseconds. The maximum load on IOCS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. Valid Address1 tsuA(IOWR) tw(IOWR) thA(IOWR) IORW# IOCS16# tdfIOCS16(ADR) tsu(IOWR) Din Valid 1. Valid Address consists of signals CS1FX#, CS3FX#, and A2-A0. tdrIOCS16(ADR) th(IOWR) D15-D0 519 ILL2-8.4 FIGURE 2-2: I/O WRITE TIMING DIAGRAM VIHT VHT INPUT REFERENCE POINTS VHT OUTPUT VLT VILT VLT 519 ILL F11.0 AC test inputs are driven at VIHT (2.4V) for a logic "1" and VILT (0.4V) for a logic "0". Measurement reference points for inputs and outputs are VHT (2.0V) and VLT (0.8V). Input rise and fall times (10% 90%) are <10 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 2-3: AC INPUT/OUTPUT REFERENCE WAVEFORMS (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 13 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 2.4 I/O Transfer Function 2.4.1 I/O Function ADM permits 8-bit data access if the user issues a Set Feature Command to enable 8-bit Mode. The following table defines the function of various operations. TABLE 2-7: I/O FUNCTION CS3FX# VIL VIH VIH VIH VIH VIH VIL VIL VIL CS1FX# VIL VIH VIL VIL VIL VIL VIH VIH VIH A0-A2 X1 X 1-7H 1-7H 0 0 6H 6H 7H IORD# X X VIH VIL VIH VIL VIH VIL VIL IOWR# X X VIL VIH VIL VIH VIL VIH VIH D15-D8 Undefined High Z X High Z In2 Out2 X High Z High Z D7-D0 Undefined High Z Data In Data Out In Out Control In Status Out Data Out T2-7.1 519 Function Code Invalid Mode Standby Mode Task File Write Task File Read Data Register Write Data Register Read Control Register Write Alt Status Read Drive Address 1. X can be VIL or VIH, but no other value. 2. If 8-bit data transfer mode is enabled. In 8-bit data transfer mode, High Byte is undefined for Data Out, can be VIL or VIH, but no other value, for Data In. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 14 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.0 SOFTWARE INTERFACE 3.1 ATA-Disk Module Drive Register Set Definitions and Protocol 3.1.1 ATA-Disk Module Addressing The I/O decoding for an ADM is as follows: TABLE 1 1 1 1 1 1 1 1 0 0 3-1: TASK REGISTERS CS1FX# 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 IORD# = 0 RD Data Error Register Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Alt Status Drive Address IOWR# = 0 WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Device Control Reserved T3-1.0 519 CS3FX# 3.1.2 ATA-Disk Module Registers The following section describes the hardware registers used by the host software to issue commands to the ADM. These registers are often collectively referred to as the "Task File Registers." 3.1.2.1 Data Register This 16-bit register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command. Data transfer can be performed in PIO mode. 3.1.2.2 Error Register (Read Only) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows: D7 BBK D6 UNC D5 0 D4 IDNF D3 0 D2 ABRT D1 0 D0 AMNF Bit 7 (BBK) Bit 6 (UNC) Bit 5 Bit 4 (IDNF) Bit 3 Bit 2 (Abort) Bit 1 This bit is set when a Bad Block is detected. This bit is set when an Uncorrectable Error is encountered. This bit is 0. The requested sector ID is in error or cannot be found. This bit is 0. This bit is set if the command has been aborted because of an ADM status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. This bit is 0. Bit 0 (AMNF) This bit is set in case of a general error. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 15 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.1.2.3 Feature Register (Write Only) This register provides information regarding features of the ADM that the host can utilize. 3.1.2.4 Sector Count Register This register contains the numbers of sectors of data requested to be transferred on a Read or Write operation between the host and the ADM. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. 3.1.2.5 Sector Number (LBA 7-0) Register This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any ADM data access for the subsequent command. 3.1.2.6 Cylinder Low (LBA 15-8) Register This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of then Logical Block Address. 3.1.2.7 Cylinder High (LBA 23-16) Register This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address. 3.1.2.8 Drive/Head (LBA 27-24) Register The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined as follows: D7 1 D6 LBA D5 1 D4 D3 D2 D1 D0 DRV HS3 HS2 HS1 HS0 Bit 7 Bit 6 This bit is set to 1. LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows: LBA7-LBA0: Sector Number Register D7-D0. LBA15-LBA8: Cylinder Low Register D7-D0. LBA23-LBA16: Cylinder High Register D7-D0. LBA27-LBA24: Drive/Head Register bits HS3-HS0. Bit 5 Bit 4 (DRV) Bit 3 (HS3) Bit 2 (HS2) Bit 1 (HS1 Bit 0 (HS0) This bit is set to 1. DRV is the drive number. When DRV=0 (Master), Master is selected. When DRV=1(Slave), Slave is selected. When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 16 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.1.2.9 Status & Alternate Status Registers (Read Only) These registers return the ADM status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits are described as follows: D7 BUSY D6 RDY D5 DWF D4 D3 D2 D1 D0 DSC DRQ CORR 0 ERR Bit 7 (BUSY) The busy bit is set when the ADM has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. Bit 6 (RDY) Bit 5 (DWF) Bit 4 (DSC) Bit 3 (DRQ) RDY indicates whether the device is capable of performing ADM operations. This bit is cleared at power up and remains cleared until the ADM is ready to accept a command. This bit, if set, indicates a write fault has occurred. This bit is set when the ADM is ready. The Data Request is set when the ADM requires that information be transferred either to or from the host through the Data register. Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector Read operation. Bit 1 (IDX) Bit 0 (ERR) This bit is always set to 0. This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers. 3.1.2.10 Device Control Register (Write Only) This register is used to control the ADM interrupt request and to issue a software Reset. This register can be written to even if the device is BUSY. The bits are defined as follows: D7 X D6 X D5 X D4 D3 D2 D1 D0 X 1 SW Rst -IEn 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 This bit is an X (don't care). This bit is an X (don't care). This bit is an X (don't care). This bit is an X (don't care). This bit is ignored by the ADM. Bit 2 (SW Rst) This bit is set to 1 in order to force the ADM to perform a software Reset operation. The chip remains in Reset until this bit is reset to `0.' Bit 1 (-IEn) Bit 0 The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the ADM are disabled. This bit is Reset to 0 at power on and Reset. This bit is ignored by the ADM. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 17 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.1.2.11 Drive Address Register (Read Only) This register contains the inverted drive select and head select addresses of the currently selected drive. The bits in this register are as follows: D7 D6 D5 D4 D3 D2 D1 D0 HiZ Bit 7 -WTG -HS3 This bit is HiZ. -HS2 -HS1 -HS0 -DS1 -DS0 Bit 6 (-WTG) This bit is 0 when a Write operation is in progress, otherwise, it is 1. Bit 5 (-HS3) Bit 4 (-HS2) Bit 3 (-HS1) Bit 2 (-HS0 Bit 1 (-DS1) Bit 0 (-DS0) This bit is the negation of bit 3 in the Drive/Head register. This bit is the negation of bit 2 in the Drive/Head register. This bit is the negation of bit 1 in the Drive/Head register. This bit is the negation of bit 0 in the Drive/Head register. This bit is 0 when drive 1 is active and selected. This bit is 0 when drive 0 is active and selected. 3.1.2.12 Command Register (Write Only) This register contains the command code being sent to the drive. Command execution begins immediately after this register is written. The executable commands, the command codes, and the necessary parameters for each command are listed in Table 3-2. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 18 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2 ATA-Disk Module Command Description This section defines the software requirements and the format of the commands the host sends to the ADM. Commands are issued to the ADM by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command Register. The manner in which a command is accepted varies. There are three classes (see Table 3-2) of command acceptance, all dependent on the host not issuing commands unless the ADM is not busy (BSY=0). 3.2.1 ATA-Disk Module Command Set Table 3-2 summarizes the ADM command set with the paragraphs that follow describing the individual commands and the task file for each. TABLE Class 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 2 3 1. 2. 3. 4. 5. 6. 7. 8. 3-2: ATA-DISK MODULE COMMAND SET Command Check Power Mode Execute Drive Diagnostic Format Track Identify Drive Idle Idle Immediate Initialize Drive Parameters Read Buffer Read Long Sector Read Multiple Read Sector(s) Read Verify Sector(s) Recalibrate Seek Set Features Set Multiple Mode Set Sleep Mode Stand By Stand By Immediate Write Buffer Write Long Sector Write Multiple Write Sector(s) Write Verify Code E5H or 98H 90H 50H ECH E3H or 97H E1H or 95H 91H E4H 22H or 23H C4H 20H or 21H 40H or 41H 1XH 7XH EFH C6H E6H or 99H E2H or 96H E0H or 94H E8H 32H or 33H C5H 30H or 31H 3CH FR1 Y SC2 Y7 Y Y Y Y Y Y Y Y Y SN3 Y Y Y Y Y Y Y Y Y CY4 Y Y Y Y Y Y Y Y Y Y DH5 D8 D Y8 D D D Y D Y Y Y Y D Y D D D D D D Y Y Y Y LBA6 Y Y Y Y Y Y Y Y Y Y T3-2.0 519 FR - Features Register SC - Sector Count Register SN - Sector Number Register CY - Cylinder Registers DH - Drive/Head Register LBA - Logical Block Address Mode Supported (see command descriptions for use) Y - The register contains a valid parameter for this command. For the Drive/Head Register: Y means both the ADC and Head parameters are used; D means only the ADC parameter is valid and not the Head parameter. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 19 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.1 Check Power Mode - 98H or E5H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 98H or E5H This command checks the power mode. Because SST ADM can recover from sleep in 200 ns, Idle Mode is never enabled. ADM sets BSY, sets the Sector Count Register to 00H, clears BSY and generates an interrupt. 3.2.1.2 Execute Drive Diagnostic - 90H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 90H X 3 2 1 0 This command performs the internal diagnostic tests implemented by the ADM. If the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with status for both devices. The Diagnostic codes shown in Table 3-3 are returned in the Error Register at the end of the command. TABLE Code 01H 02H 03H 04H 05H 8XH 3-3: DIAGNOSTIC CODES Error Type No Error Detected Formatter Device Error Sector Buffer Error ECC Circuitry Error Controlling Microprocessor Error Slave Error T3-3.0 519 (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 20 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.3 Format Track - 50H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) Count (LBA mode only) X 7 6 5 4 50H Head (LBA 27-24) 3 2 1 0 This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFH or 00H). To remain host backward compatible, the ADM expects a sector buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by the ADM. If LBA=1 then the number of sectors to format is taken from the Sec Cnt register (0=256). The use of this command is not recommended. 3.2.1.4 Identify Drive - ECH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X X X Drive X X X X X 7 6 5 4 ECH X 3 2 1 0 The Identify Drive command enables the host to receive parameter information from the ADM. This command has the same protocol as the Read Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table 3-4. All reserved bits or words are zero. Table 3-4 is the definition for each field in the Identify Drive Information. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 21 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information TABLE 3-4: IDENTIFY DRIVE INFORMATION Default Value 044AH XXXXH 0000H 00XXH 0000H 0000H XXXXH XXXXH XXXXH aaaa1 0002H XXXXH 0004H aaaa1 aaaa1 000XH 0000H 0200H 0000H 0X00H 0000H 000XH XXXXH XXXXH XXXXH XXXXH 010XH XXXXH 0000H 00XXH 0000H XXXXH XXXXH 0000H 0000H 0000H Total Bytes 2 2 2 2 2 2 2 4 2 20 2 2 2 8 40 2 2 2 2 2 2 2 2 2 2 4 2 4 4 2 4 2 2 138 64 192 Data Field Type Information General configuration bit-significant information Default number of cylinders Reserved Default number of heads Reserved Reserved Default number of sectors per track Number of sectors per card (Word 7 = MSW, Word 8 = LSW) Vendor Unique Serial number in ASCII. Big Endian Byte Order in Word Buffer type Buffer size in 512 Byte increments # of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII. Big Endian Byte Order in Word Model number in ASCII. Big Endian Byte Order in Word Maximum number of sectors on Read/Write Multiple command Reserved Capabilities Reserved PIO data transfer cycle timing mode Reserved Translation parameters are valid Current numbers of cylinders Current numbers of heads Current sectors per track Current capacity in sectors (LBAs) (Word 57 = LSW, Word 58 = MSW) Multiple sector setting Total number of sectors addressable in LBA Mode Reserved (DMA Data Transfer is not supported in ADM) Advanced PIO Transfer Mode Supported Reserved Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Reserved Vendor unique bytes Reserved T3-4.2 519 Word Address 0 1 2 3 4 5 6 7-8 9 10-19 20 21 22 23-26 27-46 47 48 49 50 51 52 53 54 55 56 57-58 59 60-61 62-63 64 65-66 67 68 69-127 128-159 160-255 1. aaaa - any SST specific number (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 22 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.4.1 General Configuration This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a transfer rate greater than 10 MByte/sec and is not MFM encoded. 3.2.1.4.2 Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. 3.2.1.4.3 Default Number of Heads This field contains the number of translated heads in the default translation mode. 3.2.1.4.4 Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode. 3.2.1.4.5 Number of Sectors This field contains the number of sectors per ADM. This double word value is also the first invalid address in LBA translation mode. 3.2.1.4.6 Memory Serial Number The contents of this field are right justified and padded with spaces (20H). 3.2.1.4.7 Buffer Type This field defines the buffer capability: 0002H: a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the ADM. 3.2.1.4.8 Buffer Size This field defines the buffer capacity in 512 Byte increments. SST's ADM has up to 2 sector data buffer for host interface. 3.2.1.4.9 ECC Count This field defines the number of ECC bytes used on each sector in the Read and Write Long commands. 3.2.1.4.10 Firmware Revision This field contains the revision of the firmware for this product. 3.2.1.4.11 Model Number This field contains the model number for this product and is left justified and padded with spaces (20H). 3.2.1.4.12 Read/Write Multiple Sector Count This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands. 3.2.1.4.13 Capabilities Bit 13: Standby Timer Bit 11: IORDY Support Bit 9: LBA support Bit 8: DMA Support Set to 0, forces sleep mode when host is inactive. Set to 0, indicates that this device may support IORDY operation. Set to 1, SST's ADMs support LBA mode addressing. This bit is set to 0. DMA mode is not supported. 3.2.1.4.14 PIO Data Transfer Cycle Timing Mode This field defines the mode for PIO data transfer. ADM supports up to PIO Mode-4. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 23 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.4.15 Translation Parameters Valid If bit 0 is 1, it indicates that words 54 to 58 are valid and reflect the current number of cylinders, heads and sectors. If bit 1 is 1, it indicates that words 64 to 70 are valid to support PIO Mode-3 and 4. 3.2.1.4.16 Current Number of Cylinders, Heads, Sectors/Track These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode. 3.2.1.4.17 Current Capacity This field contains the product of the current cylinders times heads times sectors. 3.2.1.4.18 Multiple Sector Setting This field contains a validity flag in the Odd Byte and the current number of sectors that can be transferred per interrupt for R/W Multiple in the Even Byte. The Odd Byte is always 01H which indicates that the Even Byte is always valid. The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this word by default contains a 00H which indicates that R/W Multiple commands are not valid. 3.2.1.4.19 Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the ADM in LBA mode only. 3.2.1.4.20 Advanced PIO Data Transfer Mode ADM supports up to PIO Mode-4. 3.2.1.4.21 Minimum PIO Transfer Cycle Time Without Flow Control The ADM's minimum cycle time is 120 ns. 3.2.1.4.22 Minimum PIO Transfer Cycle Time with IORDY The ADM's minimum cycle time is 120 ns, e.g., PIO Mode-4. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 24 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.5 Idle - 97H or E3H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X Timer Count (5 msec increments) X 3 2 X 1 0 97H or E3H This command causes the ADM to set BSY, enter the Idle Mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is also enabled, the timer count is set to 3, with each count being 5 ms. Note that this time base (5 msec) is different from the ATA specification. 3.2.1.6 Idle Immediate - 95H or E1H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 95H or E1H This command causes the ADM to set BSY, enter the Idle Mode, clear BSY and generate an interrupt. 3.2.1.7 Initialize Drive Parameters - 91H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 0 X Drive X X X Number of Sectors X 7 6 5 4 91H Max Head (no. of heads-1) 3 2 1 0 This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Drive/Head registers are used by this command. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 25 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.8 Read Buffer - E4H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E4H X 3 2 1 0 The Read Buffer command enables the host to read the current contents of the ADM's sector buffer. This command has the same protocol as the Read Sector(s) command 3.2.1.9 Read Multiple - C4H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 C4H Head (LBA 27-24) 3 2 1 0 The Read Multiple command is similar to the Read Sector(s) command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Command execution is identical to the Read Sectors operation except that the number of sectors defined by a Set Multiple command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Read Multiple command. When the Read Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where n = remainder (sector count/block count). If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 26 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. 3.2.1.10 Read Long Sector - 22H or 23H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 3 2 1 0 22H or 23H Head (LBA 27-24) The Read Long command performs similarly to the Read Sector(s) command except that it returns 516 Bytes of data instead of 512 Bytes. During a Read Long command, the ADM does not check the ECC bytes to determine if there has been a data error. Only single sector read long operations are supported. The transfer consists of 512 Bytes of data transferred in Word-Mode followed by 4 Bytes of ECC data transferred in Byte-Mode. This command has the same protocol as the Read Sector(s) command. Use of this command is not recommended. 3.2.1.11 Read Sectors - 20H or 21H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 20H or 21H Head (LBA 27-24) This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued and after each sector of data (except the last one) has been read by the host, the ADM sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 Bytes of data from the buffer. At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 27 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.12 Read Verify Sector(s) - 40H or 41H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 40H or 41H Head (LBA 27-24) This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the ADM sets BSY. When the requested sectors have been verified, the ADM clears BSY and generates an interrupt. Upon command completion, the Command Block Registers contain the cylinder, head, and sector number of the last sector verified. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count Register contains the number of sectors not yet verified. 3.2.1.13 Recalibrate - 1XH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive X X X X X 7 6 5 4 1XH X 3 2 1 0 This command is effectively a NOP command to the ADM and is provided for compatibility purposes. 3.2.1.14 Seek - 7XH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) X X 7 6 5 4 7XH Head (LBA 27-24) 3 2 1 0 This command is effectively a NOP command to the ADM although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 28 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.15 Set Features - EFH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X Config Feature 7 6 5 4 EFH X 3 2 1 0 This command is used by the host to establish or select certain features. Table 3-5 defines all features that are supported. TABLE 01H 55H 66H 69H 81H 96H 97H 9AH BBH CCH 3-5: FEATURES SUPPORTED Operation Enable 8-bit data transfers. Disable Read Look Ahead. Disable Power on Reset (POR) establishment of defaults at software Reset. NOP - Accepted for backward compatibility. Disable 8-bit data transfer. NOP - Accepted for backward compatibility. NOP - Accepted for backward compatibility. NOP - accepted for compatibility. 4 Bytes of data apply on Read/Write Long commands. Enable Power on Reset (POR) establishment of defaults at software Reset. T3-5.1 519 Feature Features 01H and 81H are used to enable and clear 8-bit data transfer mode. If the 01H feature command is issued all data transfers will occur on the low order D7-D0 data bus and the IOCS16# signal will not be asserted for data register accesses. Features 55H and BBH are the default features for the ADM; thus, the host does not have to issue this command with these features unless it is necessary for compatibility reasons. Features 66H and CCH can be used to enable and disable whether the Power On Reset (POR) Defaults will be set when a software Reset occurs. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 29 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.16 Set Multiple Mode - C6H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X Sector Count X 7 6 5 4 C6H X 3 2 1 0 This command enables the ADM to perform Read and Write Multiple operations and establishes the block count for these commands. The Sector Count Register is loaded with the number of sectors per block. Upon receipt of the command, the ADM sets BSY to 1 and checks the Sector Count Register. If the Sector Count Register contains a valid value and the block count is supported, the value is loaded for all subsequent Read Multiple and Write Multiple commands and execution of those commands is enabled. If a block count is not supported, an Aborted Command error is posted, and Read Multiple and Write Multiple commands are disabled. If the Sector Count Register contains 0 when the command is issued, Read and Write Multiple commands are disabled. At power on, or after a hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read and Write Multiple disabled. 3.2.1.17 Set Sleep Mode - 99H or E6H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 99H or E6H This command causes the ADM to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted but not required). Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 15 milliseconds. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 30 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.18 Standby - 96H or E2H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 96H or E2H This command causes the ADM to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). 3.2.1.19 Standby Immediate - 94H or E0H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 94H or E0H This command causes the ADM to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). 3.2.1.20 Write Buffer - E8H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E8H X 3 2 1 0 The Write Buffer command enables the host to overwrite contents of the ADM's sector buffer with any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 Bytes. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 31 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.1.21 Write Long Sector - 32H or 33H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 3 2 1 0 32H or 33H Head (LBA 27-24) This command is similar to the Write Sector(s) command except that it writes 516 Bytes instead of 512 Bytes. Only single sector Write Long operations are supported. The transfer consists of 512 Bytes of data transferred in Word-Mode followed by 4 Bytes of ECC transferred in Byte-Mode. Because of the unique nature of the solid-state ADM, the 4 Bytes of ECC transferred by the host may be used by the ADM. The ADM may discard these 4 Bytes and write the sector with valid ECC data. This command has the same protocol as the Write Sector(s) command. Use of this command is not recommended. 3.2.1.22 Write Multiple Command - C5H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X LBA X Drive Cylinder High Cylinder Low Sector Number Sector Count X 7 6 5 4 C5H Head 3 2 1 0 Note: The current revision of the SST ADM can support up to a block count of 1 as indicated in the Identify Drive Command information. This command is similar to the Write Sectors command. The ADM sets BSY within 400 ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the Write Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command. When the Write Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = remainder (sector count/block count) If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when Write Multiple commands are disabled, the Write Multiple operation will be rejected with an aborted command error. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 32 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information Errors encountered during Write Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count Register contains the residual number of sectors that need to be transferred for successful completion of the command e.g. each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count Register contains 6 and the address is that of the third sector. 3.2.1.23 Write Sector(s) - 30H or 31H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 30H or 31H Head (LBA 27-24) This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is accepted, the ADM sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. 3.2.1.24 Write Verify - 3CH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 3CH Head (LBA 27-24) 3 2 1 0 This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write Sector(s) command. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 33 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 3.2.2 Error Posting The following table summarizes the valid status and error value for all the ADM Command set. TABLE 3-6: ERROR AND STATUS REGISTER Error Register Status Register AMNF DRDY V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V DWF V DSC V V V V V V V V V V V V V V V V V V V V V V V V V V V V CORR ERR V V V V V V V V V V V V V V V V V V V V V V V V V T3-6.0 519 Command Check Power Mode Execute Drive Format Track Identify Drive Idle Idle Immediate Initialize Drive Parameters Read Buffer Read Multiple Read Long Sector Read Sector(s) Read Verify Sectors Recalibrate Seek Set Features Set Multiple Mode Set Sleep Mode Standby Standby Immediate Write Buffer Write Long Sector Write Multiple Write Sector(s) Write Verify Invalid Command Code 1. See Table 3-3 Note: V = valid on this command BBK Diagnostic1 UNC IDNF ABRT V (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 34 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 4.0 APPENDIX 4.1 Differences between ATA-Disk Module and ATA/ATAPI-5 Specifications This section details differences between ADM vs. ATA. 4.1.1 Electrical Differences 4.1.1.1 TTL Compatibility ADM is not TTL compatible, it is a purely CMOS interface. Refer to Section 2.3.2 of this specification. 4.1.1.2 Pull Up Resistor Input Leakage Current The minimum pull up resistor input leakage current is 50K ohms rather than the 10K ohms stated in the ATA specification. 4.1.2 Functional Differences 4.1.2.1 Idle Timer The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value specified in ATA specifications. 4.1.2.2 Recovery from Sleep Mode For ADM devices, recovery from sleep mode is accomplished by simply issuing another command to the device. A hardware or software reset is not required. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 35 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 5.0 PHYSICAL DIMENSIONS 51.0 25.5 3.2 3.5 4.5 26.0 5.34 1.0 6.0 7.52 Note: All units are in mm Tolerance: 0.2 mm unless otherwise specified 40-fem-right-angle.2 40-PIN FEMALE RIGHT ANGLE CONNECTOR SST PACKAGE CODE: FRI 5.34 51.0 1.0 4.5 24.0 8.5 6.0 Note: All units are in mm Tolerance: 0.2 mm unless otherwise specified 40-fem-straight-conn.2 8.5 40-PIN FEMALE STRAIGHT CONNECTOR SST PACKAGE CODE: FSI (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 36 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 45.0 22.5 3.2 3.0 4.0 5.3 28.0 2.91 1.48 2.46 3.91 1.0 4.6 4.0 Note: All units are in mm Tolerance: 0.2 mm unless otherwise specified 44-fem-right-angle.3 44-PIN FEMALE RIGHT ANGLE CONNECTOR SST PACKAGE CODE: FRJ 1.0 5.3 4.0 24.0 4.0 44.4 45.0 Note: All units are in mm Tolerance: 0.2 mm unless otherwise specified 4.0 44-fem-straight-conn.3 44-PIN FEMALE STRAIGHT CONNECTOR SST PACKAGE CODE: FSJ (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 37 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 6.0 PRODUCT ORDERING INFORMATION SST 58 XX SM XX 192 XXX 70 XXX C X FR J XX X Package Modifier I = 40-pin connector J = 44-pin connector Package Type FR = Female Right Angle FS = Female Straight Operation Temperature C = Commercial: 0C to +70C Data Transfer Speed 70 = 70 ns, supports up to PIO Mode-4 Device Density 192 = 192 MByte 128 = 128 MByte 096 = 96 MByte 064 = 64 MByte 048 = 48 MByte 032 = 32 MByte 024 = 24 MByte 016 = 16 MByte 008 = 8 MByte Module Voltage S = 5.0V L = 3.3V Device Family 6.1 Valid Combinations Valid combinations for SST58SM008 SST58SM008-70-C-FRI SST58LM008-70-C-FRI SST58SM008-70-C-FSI SST58LM008-70-C-FSI SST58SM008-70-C-FRJ SST58LM008-70-C-FRJ SST58SM008-70-C-FSJ SST58LM008-70-C-FSJ Valid combinations for SST58LM008 Valid combinations for SST58SM016 SST58SM016-70-C-FRI SST58LM0016-70-C-FRI SST58SM016-70-C-FSI SST58LM0016-70-C-FSI SST58SM016-70-C-FRJ SST58LM0016-70-C-FRJ SST58SM016-70-C-FSJ SST58LM0016-70-C-FSJ Valid combinations for SST58LM016 (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 38 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information Valid combinations for SST58SM024 SST58SM024-70-C-FRI SST58LM024-70-C-FRI SST58SM024-70-C-FSI SST58LM024-70-C-FSI SST58SM024-70-C-FRJ SST58LM024-70-C-FRJ SST58SM024-70-C-FSJ SST58LM024-70-C-FSJ Valid combinations for SST58LM024 Valid combinations for SST58SM032 SST58SM032-70-C-FRI SST58LM032-70-C-FRI SST58SM032-70-C-FSI SST58LM032-70-C-FSI SST58SM032-70-C-FRJ SST58LM032-70-C-FRJ SST58SM032-70-C-FSJ SST58LM032-70-C-FSJ Valid combinations for SST58LM032 Valid combinations for SST58SM048 SST58SM048-70-C-FRI SST58LM048-70-C-FRI SST58SM048-70-C-FSI SST58LM048-70-C-FSI SST58SM048-70-C-FRJ SST58LM048-70-C-FRJ SST58SM048-70-C-FSJ SST58LM048-70-C-FSJ Valid combinations for SST58LM048 Valid combinations for SST58SM064 SST58SM064-70-C-FRI SST58LM064-70-C-FRI SST58SM064-70-C-FSI SST58LM064-70-C-FSI SST58SM064-70-C-FRJ SST58LM064-70-C-FRJ SST58SM064-70-C-FSJ SST58LM064-70-C-FSJ Valid combinations for SST58LM064 Valid combinations for SST58SM096 SST58SM096-70-C-FRI SST58LM096-70-C-FRI SST58SM096-70-C-FSI SST58LM096-70-C-FSI SST58SM096-70-C-FRJ SST58LM096-70-C-FRJ SST58SM096-70-C-FSJ SST58LM096-70-C-FSJ Valid combinations for SST58LM096 Valid combinations for SST58SM128 SST58SM128-70-C-FRI SST58LM128-70-C-FRI SST58SM128-70-C-FSI SST58LM128-70-C-FSI SST58SM128-70-C-FRJ SST58LM128-70-C-FRJ SST58SM128-70-C-FSJ SST58LM128-70-C-FSJ Valid combinations for SST58LM128 Valid combinations for SST58SM192 SST58SM192-70-C-FRI SST58LM192-70-C-FRI Note: SST58SM192-70-C-FSI SST58LM192-70-C-FSI SST58SM192-70-C-FRJ SST58LM192-70-C-FRJ SST58SM192-70-C-FSJ SST58LM192-70-C-FSJ Valid combinations for SST58LM192 Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 39 ATA-Disk Module SST58SM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LM008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 Advance Information 7.0 LIMITED WARRANTY SST warrants all products against non-conformances in materials and workmanship for a period of one year from the delivery date of subject products. SST's liability is limited to replacing or repairing the product if it has been paid for. SST's warranties will not be affected by rendering of technical advice in connection with the order of products furnished hereunder. Except as expressly provided above, SST makes no warranties, express or implied, including without limitation any warranty of merchantability or fitness for a particular purpose. In no event shall SST be liable for any incidental or consequential damages with respect to the products purchased hereunder. SST reserves the right to discontinue production or change specifications or change prices at any time and without notice. The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice. SST assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the information provided herein. SST assumes no responsibility for the use of any circuitry other than circuitry embodied in an SST product; no other circuits, patents, or licenses are implied. SST assumes no responsibility for the functioning of features or parameters not described herein. 7.1 Life Support Policy SST's products are not authorized for use as critical component in life support devices or systems. Life support devices or systems are devices or systems that, (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be expected to cause the failure of the life support device or system, or the affect its safety or effectiveness. 7.2 Patent Protection SST products are protected by assigned U.S. and foreign patents. Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com (c)2001 Silicon Storage Technology, Inc. S71193-01-000 9/01 519 40 |
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